1. Field of the Invention
The invention relates to a magnetic random access memory (MRAM), and, more particularly, to increasing the performance of read and write operations to MRAM cells of a memory array.
2. Description of the Prior Art
Magnetic random access memory (MRAM) shows significant promise in the world of memory and other storage, such as to replace solid state. It is expected that MRAM will replace conventional non-volatile memory and solid state storage and perhaps even other types of storage in the near years ahead. However, great strides are to first be made before wider adoption and popularity of MRAMs, as this type of memory is still in its infancy.
Among other challenges, memory systems utilizing MRAMs face performance issues during read and write operations. Generally, MRAM, such as magnetic tunnel junction (MTJ) is paired with an access transistor that directs the reading from and writing to the MTJ. The access transistor is typically coupled to a word line of the memory system or array and a bit line and a sense line are coupled to the MTJs of the array for accessing and reading and writing thereof, under the direction of access transistors. However, only one MTJ of a column of MTJs that are all connected to the same bit line can be read and/or written at any given time. When any other MTJ of the same column is to be accessed for reading and writing operations, the MTJ that is being programmed or read must be released prior to programming or reading of any other MTJ that is coupled to a common bit line. In some memory applications it would be beneficial to read and write the same cell via different ports. There could be two or more ports that the memory can be read or written to. As an example one such memory can be read by the CPU while it is being written into by another device. As is appreciated, this would require extra rows and columns in order to access the same cell from different ports.
Therefore, in light of the foregoing, what is needed is a memory array, made of, at least in part, MRAMs with read and write capability from different ports.